OASYS: a framework for analog circuit synthesis

We describe a hierarchical structure for a knowledge-based analog circuit synthesis tool. Analog circuit topologies are represented as a hierarchy of abstract functional blocks each with associated design knowledge. We also describe mechanisms to select from among alternate design styles, and to translate performance specifications from one level in the hierarchy to the next lower level. A prototype implementation, OASYS, synthesizes sized transistor schematics for CMOS operational amplifiers and comparators from a set of performance specifications and process parameters. We describe the role such a synthesis system can play in exploring the space of designable circuits. And finally, we briefly describe other related research in analog synthesis at Carnegie Mellon, including OASYSVM, which facilitates the addition of new design topologies to the framework, and ANAGRAM, the counterpart to OASYS, which performs the circuit schematic to physical layout phase of analog circuit design